This year, Intel will release Sapphire Rapids server processors based on the 10nm process technology and the Golden Cove architecture.

We have known for a long time that these CPUs will be multi-chip. More specifically, they will contain four chips, which Intel itself calls tiles. Each tile will have 15 cores, that is, in total we are talking about 60 cores. But all the data indicate that Intel will not release 60-core models, but will limit itself to 56 cores.

Today, technical details about the internal structure of these CPUs appeared on the Web.

So, each CPU tile is actually a separate full-fledged processor with an integrated northbridge, memory and PCIe interfaces, as well as other I / O interfaces. There are also five EMIB bridges allocated to each tile.

Within each tile, the layer layout is similar to several previous generations of Intel enterprise processors. Intel uses the Mesh connection and places various IP blocks on the mesh, connecting them into a ring bus network. Each tile contains 15 CPU cores, each with 2 MB of dedicated L2 cache and 1.875 MB of L3 cache chunk, which provides a total of 28.125 MB of L3 cache. It is shared by all 60 cores of the kernel. The total L3 cache for the CPU is 112.5 MB. Each tile also has a memory controller unit with 128-bit (160-bit including ECC) DDR5 memory.

The PCIe/CXL interface for Sapphire Rapids is huge. Each tile is equipped with a PCIe 5.0 and CXL 1.1 root complex with 32 lanes, which equates to 128 PCI-Express Gen 5 or CXL 1.1 lanes.

bbabo.Net