At the last ISSCC conference, Intel, among other things, spoke about the upcoming Ponte Vecchio accelerator. Recall that this is a specialized graphics processor based on the Xe architecture.

It’s worth starting with the fact that if Intel previously talked about 47 tiles that make up the GPU, now the company claims 63 tiles. But it's not that the company has redesigned the GPU - it would be impossible for such a short period. The bottom line is that Ponte Vecchico really has 47 functional tiles. The remaining 16 are called thermal tiles and are responsible for regulating the power consumption of this monstrous GPU. Recall that the TDP of this solution is 600 watts.

Thermal tiles are located in places where the main tiles do not have contact with the top layer. The thermal plate must absorb heat and transfer it to the heat spreader located above. Simply put, these are silicon inserts designed to align the upper border of the entire GPU and ensure normal contact with the heat distribution cover.

Returning to the basic configuration, we now know in detail how many of which tiles the GPU has. 16 are directly computed, eight are used for RAMBO cache, two are Foveros base technology tiles, two are Xe-Link interface tiles, eight are HBM2E memory tiles, and the EMIB connection occupies 11 tiles.

RAMBO is a new SRAM technology that uses four 3.75MB blocks (15MB total) per tile. They are connected to the bus at 1.3 TB/s per tile. The compute tiles are connected via a 2.6 TB/s bus.

The 47 basic tiles have a total area of ​​2330 mm², with thermal tiles the total area increases to 3100 mm². The area of ​​the entire GPU with packaging is 4,844 mm².

For compute tiles, Intel uses the TSMC N5 process, Xe-Link tiles use the TSMC N7 process, and RAMBO cache uses the Intel 7 process.

By the way, the above TDP of 600 W is the value when using liquid cooling, and when using air, the figure is 450 W.

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